This invention relates to a television receiver in which an input video signal is processed in a digital signal processing circuit, and an electron beam is scanned at a frequency which is n times (n being an integer) as high as that of a horizontal synchronizing signal of the video signal. More particularly, this invention relates to a clock generating circuit for use in such a television receiver to generate a system clock signal synchronized with the horizontal synchronizing signal of the input video signal.
Standard television signals employed in Japan are based on the NTSC system, and there is the following relation between the frequency f.sub.sc of a color subcarrier and the frequency fH of a horizontal synchronizing signal: EQU f.sub.sc =455/2.multidot.f.sub.H. . . (1)
Therefore, when a system clock signal synchronized with the color subcarrier having the frequency f.sub.sc is used during digital signal processing of a video signal, the color signal can be conveniently demodulated. However, the relation specified in the equation (1) is not always satisfied in outputs of all of modern video apparatus. Thus, when a system clock signal synchronized with the color subcarrier is used for the purpose of digital signal processing of video signals generated as outputs from those video apparatus which do not satisfy the above relation, it is difficult to easily reproduce the horizontal synchronizing signal, and a circuit arrangement of complex structure is required. Also, because the points of sampling differ in the horizontal direction for each of individual lines, reduction of noise as by a noise reducer cannot be expected. Therefore, a system clock signal synchronized with the horizontal synchronizing signal is preferably used for the purpose of digital signal processing of the video signal outputs from those video apparatus. Also, the use of the system clock signal synchronized with the horizontal synchronizing signal is preferable in that the speed conversion of the video signal can be facilitated, and scanning at a multiple density can be made.
FIGS. 2A and 2B are block diagrams of prior art synchronizing circuits respectively exployed for generating such a synchronizing signal in a television receiver. In each of FIGS. 2A and 2B, the reference numerals 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 and 12 designate a horizontal synchronizing signal input terminal, a phase comparator (PD), a low-pass filter (LPF), a voltage controlled oscillator (VCO), a system clock output terminal, a 1/m frequency divider, a horizontal output circuit, a flyback transformer (FBT), a 1/n frequency divider, a synchronizing signal, a clock generating circuit, and a horizontal deflection circuit, respectively.
Referring to FIG. 2A, in response to the application of a horizontal synchronizing signal having a frequency f.sub.H to the horizontal synchronizing signal input terminal 1, the clock generating circuit 11 generates a system clock signal having a frequency m.times.f.sub.H, and such a clock signal appears at the system clock output terminal 5. Also, in response to the application of the horizontal synchronizing signal to the horizontal deflection circuit 12, the horizontal output circuit 7 generates a horizontal deflection pulse signal to drive a horizontal DY. As described above, the system clock signal and the horizontal deflection pulse signal are independently synchronized with the horizontal synchronizing signal and generated in parallel with each other.
Referring to FIG. 2B, in response to the application of a horizontal synchronizing signal having a frequency f.sub.H to the horizontal synchronizing signal input terminal 1, the clock generating circuit 11 generates a system clock signal which appears at the system clock output terminal 5. By dividing the frequency of the system clock signal by the factor of m by the 1/m frequency divider 6, a horizontal synchronizing signal 10 having a scanning frequency 2.times.f.sub.H is obtained and applied to the horizontal deflection circuit 12. In the horizontal deflection circuit 12, the horizontal output circuit 7 generates a horizontal deflection pulse signal synchronous with this synchronizing signal 10 to drive a horizontal DY. Thus, in the form shown in FIG. 2B, two PLL circuits are connected in series with each other.
As prior art systems related to the circuit arrangements shown in FIGS. 2A and 2B, those disclosed in, for example, JP-A-62-81177 and U.S. Pat. No. 4,636,861 are referenced.
However, the manners of system clock generation and horizontal deflection by the prior art circuits described above have frequently given rise to such a problem that, when an input video signal including skew or jitter is applied to a television receiver, jitter occurs on a scene being displayed, or skew is emphasized on a scene being reproduced. The reasons will be described with reference to FIGS. 3A and 3B which show step responses of the clock generating circuit 11 and horizontal deflection circuit 12 shown in each of FIGS. 2A and 2B when a phase error is present. That is, each of FIGS. 3A and 3B shows the response of the output relative to the input when a phase difference .phi. occurs at time t=0.
The case shown in FIG. 3A will be first discussed. Suppose that the step response of the clock generating circuit 11 of FIG. 2A in the presence of a phase error is represented by a solid characteristic curve as shown in FIG. 3A, while that of the horizontal deflection circuit 12 of FIG. 2A in the presence of the phase error is represented by a dotted characteristic curve as shown in FIG. 3A. The response of the signal system is determined by the response characteristic of the clock generating circuit 11, while that of the deflection system is determined by the response characteristic of the horizontal deflection circuit 12. As a result, the difference between these response characteristics appears in the form of a horizontal jitter on a scene being reproduced. Also, suppose that the step response of the clock signal generating circuit 11 of FIG. 2B in the presence of a phase error is represented by a dotted characteristic curve as shown in FIG. 3B. In FIG. 2B, the synchronizing signal 10 from the clock generating circuit 11 is applied as an input to the horizontal deflection circuit 12. As a result, the step response of the horizontal deflection circuit 12 of FIG. 2B is represented by a solid characteristic curve as shown in FIG. 3B, and skew included in an input signal tends to be emphasized on a scene being reproduced.